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2 , cmos, 5 v/+5 v spst switches adg601/adg602 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2001C2007 analog devices, inc. all rights reserved. features low on resistance, 2.5 maximum <0.65 on-resistance flatness dual 2.7 v to 5.5 v or single +2.7 v to +5.5 v supplies rail-to-rail input signal range tiny, 6-lead sot-23; 8-lead msop; and 820 m 2255 m die low power consumption ttl-/cmos-compatible inputs applications automatic test equipment power routing communication systems data acquisition systems sample-and-hold systems avionics relay replacement battery-powered systems functional block diagrams adg602 d s in adg601 d s in notes 1. switches shown for a logic 0 input. 02619-001 figure 1. table 1. truth table adg601 in adg602 in switch condition 0 1 off 1 0 on general description the adg601/adg602 are monolithic, cmos single-pole single-throw (spst) switches with on resistance typically less than 2.5 . the low on-resistance flatness makes the adg601/adg602 ideally suited to many applications, particularly those requiring low distortion. these switches are ideal replacements for mechanical relays because they are more reliable, have lower power requirements, and are available in much smaller package sizes. the adg601 is a normally open (no) switch, and the adg602 is a normally closed (nc) switch. each switch conducts equally well in both directions when the device is on, with the input signal range extending to the supply rails. the switches are available in tiny, 6-lead sot-23; 8-lead msop; and 820 m 2255 m die. product highlights 1. low on resistance (2 typical) 2. dual 2.7 v to 5.5 v or single +2.7 v to +5.5 v supplies 3. tiny, 6-lead sot-23; 8-lead msop; and 820 m 2255 m die 4. rail-to-rail input signal range
adg601/adg602 rev. c | page 2 of 12 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dual supply ................................................................................... 3 single supply ................................................................................. 4 absolute maximum ratings ............................................................5 esd caution...................................................................................5 pin configurations and function descriptions ............................6 typical performance characteristics ..............................................7 terminology .......................................................................................9 test circuits..................................................................................... 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 3/07rev. b to rev. c added die package.............................................................universal changes to specifications .................................................................3 added figure 4 and table 6..............................................................6 changes to ordering guide .......................................................... 11 3/06rev. a to rev. b updated format..................................................................universal changes to 6-lead sot-23 (rj-6) pin configuration .................6 added pin function descriptions table ........................................6 changes to figure 19.........................................................................9 updated outline dimensions........................................................11 changes to ordering guide ...........................................................11 6/03rev. 0 to rev. a changes to specifications.................................................................2 changes to ordering guide .............................................................4 updated outline dimensions..........................................................8
adg601/adg602 rev. c | page 3 of 12 specifications dual supply v dd = 5 v 10%, v ss = C5 v 10%, gnd = 0 v, unless otherwise noted. table 2. b version 1 parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range v ss to v dd v v dd = +4.5 v, v ss = C4.5 v on resistance (r on ) 2 typ v s = 4.5 v, i ds = ?10 ma; see figure 15 2.5 5.5 max on-resistance flatness (r flat (on) ) 0.35 0.4 typ v s = 3.3 v, i ds = ?10 ma 0.6 0.65 max leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off ) 0.01 na typ v s = +4.5 v/?4.5 v, v d = ?4.5 v/+4.5 v; see figure 16 0.25 1 na max drain off leakage, i d (off ) 0.01 na typ v s = +4.5 v/?4.5 v, v d = ?4.5 v/+4.5 v; see figure 16 0.25 1 na max channel on leakage, i d , i s (on) 0.01 na typ v s = v d = +4.5 v or ?4.5 v; see figure 17 0.25 1 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2 pf typ dynamic characteristics 2 t on 80 ns typ r l = 300 , c l = 35 pf 120 155 ns max v s = 3.3 v; see figure 18 t off 45 ns typ r l = 300 , c l = 35 pf 75 90 ns max v s = 3.3 v; see figure 18 charge injection 250 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 19 off isolation ?60 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 20 bandwidth ?3 db 180 mhz typ r l = 50 , c l = 5 pf; see figure 21 c s (off ) 50 pf typ f = 1 mhz c d (off ) 50 pf typ f = 1 mhz c d , c s (on) 145 pf typ f = 1 mhz power requirements v dd = +5.5 v, v ss = ?5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max i ss 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max 1 temperature range for b ve rsion is ?40c to +85c. 2 guaranteed by design, not subject to production test.
adg601/adg602 rev. c | page 4 of 12 single supply v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. b version 1 parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range 0 v to v dd v v dd = 4.5 v on resistance (r on ) 3.5 typ v s = 0 v to 4.5 v, i ds = ?10 ma; see figure 15 5 8 max on-resistance flatness (r flat (on) ) 0.2 0.2 typ v s = 1.5 v to 3.3 v, i ds = C10 ma 0.6 max leakage currents v dd = 5.5 v source off leakage, i s (off ) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v; see figure 16 0.25 1 na max drain off leakage, i d (off ) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v; see figure 16 0.25 1 na max channel on leakage, i d , i s (on) 0.01 na typ v s = v d = 4.5 v or 1 v; see figure 17 0.25 1 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2 pf typ dynamic characteristics 2 t on 110 ns typ r l = 300 , c l = 35 pf 220 280 ns max v s = 3.3 v; see figure 18 t off 50 ns typ r l = 300 , c l = 35 pf 80 110 ns max v s = 3.3 v; see figure 18 charge injection 20 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 19 off isolation ?60 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 20 bandwidth C3 db 180 mhz typ r l = 50 , c l = 5 pf; see figure 21 c s (off ) 50 pf typ f = 1 mhz c d (off ) 50 pf typ f = 1 mhz c d , c s (on) 145 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max 1 temperature range for b ve rsion is ?40c to +85c. 2 guaranteed by design, not subject to production test.
adg601/adg602 rev. c | page 5 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to v ss 13 v v dd to gnd ?0.3 v to +6.5 v v ss to gnd +0.3 v to C6.5 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v digital inputs 1 ?0.3 v to v dd + 0.3 v or 30 ma (whichever occurs first) continuous current, s or d 100 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 200 ma operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c thermal resistance msop ja 206c/w jc 44c/w sot-23 ja 229.6c/w jc 91.99c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature 220c 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at a time. esd caution
adg601/adg602 rev. c | page 6 of 12 pin configurations and function descriptions v dd 1 s 2 v ss 3 in 6 d 5 gnd 4 adg601/ adg602 top view (not to scale) 0 2619-002 pin 1 indicator d 1 nc 2 nc 3 v dd 4 s 8 gnd 7 in 6 v ss 5 nc = no connect adg601/ adg602 top view (not to scale) 0 2619-003 pin 1 indicator 02619-021 1 2 3 4 5 6 7 14 top view (not to scale) 13 12 11 10 9 8 figure 2. 6-lead sot-23 (rj-6) figure 3. 8-lead msop (rm-8) figure 4. die (820 m 2255 m) table 5. pin function descriptions pin no. 6-lead sot-23 8-lead msop mnemonic description 1 4 v dd most positive power supply potential. 2 8 s source terminal. can be an input or output. 3 5 v ss most negative power supply potential. 4 7 gnd ground (0 v) reference. 5 1 d drain terminal. can be an input or output. 6 6 in logic control input. n/a 2, 3 nc no connect. table 6. die pad coordinates 1 die pad coordinates die pad no. x (m) y (m) mnemonic description 1 ?265 +754 nc no connect. 2 ?265 +525 d drain terminal. can be an input or output. 2 3 ?265 +241 d drain terminal. can be an input or output. 2 4 ?265 +141 d drain terminal. can be an input or output. 2 5 ?265 ?191 nc no connect. 6 ?265 ?409 nc no connect. 7 ?265 ?549 nc no connect. 8 ?265 ?787 v dd most positive power supply potential. 9 +265 ?767 v ss most negative power supply potential. 10 +265 ?429 in logic control input. 11 +265 ?289 gnd ground (0 v) reference. 12 +265 +189 s source terminal. can be an input or output. 3 13 +265 +521 s source terminal. can be an input or output. 3 14 +265 +661 nc source terminal. can be an input or output. 1 measured from the center of the die. 2 bond the d pads together to a single point to preserve the on resistance and current handling capability. the common point act s as the drain pin of the switch. 3 bond the s pads together to a single poi nt to preserve the on resistance and curre nt handling capability. the common point act s as the source pin of the switch.
adg601/adg602 rev. c | page 7 of 12 typical performance characteristics 5 4 0 3 2 1 v d ,v s (v) t a =25c 3.3v 3v 2.5v 5v 4.5v on resistance ( ? ) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 02619-004 figure 5. on resistance vs. v d , v s (dual supply) 10 8 0 6 4 2 3 9 1 5 7 v d ,v s (v) 0 0.51.01.52.02.53.03.54.04.55.0 on resistance ( ? ) v dd =2.7v v dd =3.0v v dd =4.5v v dd =3.3v v dd =5.0v t a =25c v ss =0v 02619-005 figure 6. on resistance vs. v d , v s (single supply) 5 4 0 3 2 1 v dd =+5v v ss =?5v v d ,v s (v) ?5?4?3?2?1012345 on resistance ( ? ) +85c +25c ?40c 0 2619-006 figure 7. on resistance vs. v d , v s for different temperatures (dual supply) on resistance ( ? ) 5 4 0 3 2 1 v dd =5v v ss =0v +85c +25c ?40c v d ,v s (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 02619-007 figure 8. on resistance vs. v d , v s for different temperatures (single supply) leakage current (na) 0.5 0.3 ?0.5 0.1 ?0.1 ?0.3 ?0.2 0.4 ?0.4 0 0.2 temperature (c) 0 102030405060708085 v dd = +5v v ss = ?5v v d = 4.5v v s = 4.5v i s (off) i d , i s (on) i d (off) 02619-009 figure 9. leakage currents vs. temperature (dual supply) leakage current (na) 0.5 0.3 ?0.5 0.1 0 ?0.1 ?0.3 ?0.2 0.4 ?0.4 0.2 temperature (c) v dd = 5v v ss = 0v v d = 4.5v/1v v s = 1v/4.5v i s (off) i d (off) i d , i s (on) 0 102030405060708085 02619-008 figure 10. leakage currents vs. temperature (single supply)
adg601/adg602 rev. c | page 8 of 12 charge injection (pc) 500 400 0 300 200 100 150 450 50 250 350 v s (v) t a =25c v dd =+5v v ss =0v v dd =+5v v ss = ?5v ?5?4?3?2?1012345 0 2619-010 figure 11. charge injection vs. source voltage time (ns) 180 160 0 80 60 40 20 140 100 120 t on t off temperature (c) ?40 ?20 0 20 40 60 80 v dd =+5v v ss =0v v dd =+5v v ss =?5v v dd =+5v v ss = ?5v v dd =+5v v ss =0v 02619-011 figure 12. t on /t off times vs. temperature frequency (mhz) 0 ?10 ?80 ?20 ?30 ?70 ?40 ?50 ?60 off isolation (db) v dd =+5v v ss =?5v t a = 25c 0.2 1 10 100 02619-012 figure 13. off isol ation vs. frequency frequency (mhz) 0 ?2 ?12 ?4 ?6 ?10 ?8 on response (db) v dd =+5v v ss = ?5v t a = 25c 0.2 1 10 100 400 0 2619-013 figure 14. on response vs. frequency
adg601/adg602 rev. c | page 9 of 12 terminology v dd most positive power supply potential. v ss most negative power supply potential. i dd positive supply current. i ss negative supply current. gnd ground (0 v) reference. s source terminal. can be an input or an output. d drain terminal. can be an input or an output. in logic control input. v d , v s analog voltage on terminal d and terminal s. r on ohmic resistance between terminal d and terminal s. r flat (on) flatness is defined as the difference between the maximum and minimum values of on resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured with reference to ground. c d , c s (on) on switch capacitance. measured with reference to ground. c in digital input capacitance. t on delay between applying the digital control input and the output switching on. t off delay between applying the digital control input and the output switching off. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. on response frequency response of the on switch. insertion loss loss due to the on resistance of the switch.
adg601/adg602 rev. c | page 10 of 12 test circuits i ds v1 sd v s r on =v1/i ds 0 2619-014 figure 15. on resistance sd v s v d i s (off) i d (off) a a 0 2619-015 figure 16. off leakage sd v d i d (on) a nc nc = no connect 02619-016 figure 17. on leakage 0.1f v s in sd v dd gnd r l 300? c l 35pf v out v dd v in v in v out t on t off 50% 50% 90% 90% 50% 50% v ss v ss 0.1f adg601 adg602 02619-017 figure 18. switching times sd v dd in v s gnd c l 1nf v out r s v dd v ss v ss v in adg602 v in adg601 v out q inj =c l v out v out off on 02619-018 figure 19. charge injection network analyzer v dd v ss 0.1f 0.1f v dd v ss in v in s d off isolation = 20 log v out v s gnd 50 ? 50? r l 50? v s v out 02619-019 figure 20. off isolation network analyzer v dd v ss 0.1f 0.1f v dd v ss in v in s d insertion loss = 20 log v out with switch v s without switch gnd 50? r l 50? v s v out 02619-020 figure 21. bandwidth
adg601/adg602 rev. c | page 11 of 12 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 22. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 1 3 4 5 2 6 2.90 bsc 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 10 4 0 0.50 0.30 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.60 0.45 0.30 pin 1 indicator compliant to jedec standards mo-178-ab figure 23. 6-lead small outline transistor package [sot-23] (rj-6) dimensions shown in millimeters ordering guide model temperature range package description package option branding 1 adg601brt-reel ?40c to +85c 6-lead sot-23 rj-6 stb adg601brt-reel7 ?40c to +85c 6-lead sot-23 rj-6 stb adg601brtz-reel 2 ?40c to +85c 6-lead sot-23 rj-6 stb# adg601brtz-reel7 2 ?40c to +85c 6-lead sot-23 rj-6 stb# adg601brm ?40c to +85c 8-lead msop rm-8 stb adg601brm-reel ?40c to +85c 8-lead msop rm-8 stb adg601brm-reel7 ?40c to +85c 8-lead msop rm-8 stb ADG601BRMZ 2 ?40c to +85c 8-lead msop rm-8 s1g ADG601BRMZ-reel 2 ?40c to +85c 8-lead msop rm-8 s1g ADG601BRMZ-reel7 2 ?40c to +85c 8-lead msop rm-8 s1g adg601csurf die adg602brt-reel ?40c to +85c 6-lead sot-23 rj-6 sub adg602brt-reel7 ?40c to +85c 6-lead sot-23 rj-6 sub adg602brtz-reel 2 ?40c to +85c 6-lead sot-23 rj-6 s18 adg602brtz-reel7 2 ?40c to +85c 6-lead sot-23 rj-6 s18 adg602brm ?40c to +85c 8-lead msop rm-8 sub adg602brm-reel ?40c to +85c 8-lead msop rm-8 sub adg602brm-reel7 ?40c to +85c 8-lead msop rm-8 sub adg602brmz 2 ?40c to +85c 8-lead msop rm-8 s18 adg602brmz-reel7 2 ?40c to +85c 8-lead msop rm-8 s18 1 branding on sot-23 and msop is limited to three characters due to space constraints. 2 z = rohs compliant part, # denotes rohs compliant product, may be top or bottom marked.
adg601/adg602 rev. c | page 12 of 12 notes ?2001C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02619-0-3/07(c)

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